The TG-16 has two video control chips, a display controller and a color encoder.

Information on this page excerpted from http://archaicpixels.com/HuC6270 and http://archaicpixels.com/HuC6260.

Video Display Controller (HuC6270)

The video display controller (VDC) is the graphical workhorse of the TG-16.

Note: all VDC registers accept 16 bit values.

Specifications

64 simultaneous sprites
64KB of VRAM
a background and foreground layer

Interface

[code]

   Address   | Access | Description
   (Mapped   |  mode  |
    to $FF)  |        |

     $0000   |   R    | 6270 Status register
             |        |
             |        |   Different bits flag different conditions.
             |        |   Not all are known.
             |        |   (Note: can use special ST0 opcode to store
             |        |   an immediate value.)
             |        |     b 7 = 0
             |        |     b 6 = 'BSY' flag
             |        |         I believe this is '1' when a DMA transfer
             |        |         is happening
             |        |     b 5 = 'VD' flag
             |        |         I believe this is a '1' when Vertical Sync
             |        |         happens, otherwise a '0' (uncertain)
             |        |     b 4 = 'DV' flag (unknown)
             |        |     b 3 = 'DS' flag (unknown)
             |        |     b 2 = 'RR' flag
             |        |         Set during a Scanline interrupt (see RCR
             |        |         register)otherwise '0'
             |        |     b 1 = 'OR' flag (unknown)
             |        |     b 0 = 'CR' flag (unknown)
             |        |
     $0000   |   W    | 6270 Address register
             |        |
             |        |     b 7-5 = ignored
             |        |     b 4-0 = 6270 register number to access using
             |        |             the 6270 data registers
             |        |             ($0002 and $0003). Please see 6270
             |        |             register list (SECTION 4) for details.
             |        |
     $0002   |  R/W   | 6270 data LSB
             |        |
             |        |   Note: can use special ST1 opcode to store
             |        |         an immediate value.)
             |        |
     $0003   |  R/W   | 6270 data MSB
             |        |
             |        |   Note: can use special ST2 opcode to store
             |        |         an immediate value.)

[/code]

Status Register

A bit corresponding to one of interruption jobs is set to be "H" in the status register to make the interruption active when a cause of the interruption which is enabled by an interruption permission bit of a control register and DMA control register as showing in Figures 3G and 3Q is occurred. When the status is read from the status register, the corresponding bit is cleared automatically.

The status indicating bits are as follows.

Read Behavior

Bit(s)	Name	Description	Details
0	CR	sprite collision	Sprite #0 has collided with another sprite (1 to 63).
1	OR	sprite overflow	More than 17 sprites are detected on a single raster line. Data of a sprites which is designated are not transferred to a data buffer in a horizontal trance period. A bit of CGX in control data of a sprite by which two sprites are joined in a horizontal direction is set so that data of the sprites are not transferred to a data buffer.
2	PR	scanline interrupt	A value of a raster counter becomes a predetermined value of a raster detecting register.
3	DS	VRAM to SATB end of transfer.	Data transfer between the VRAM and sprite attribute table buffer is finished.
4	DV	VRAM DMA end of transfer	Data transfer between two regions of VRAM has finished.
5	VD	vertical blanking	The VRAM accessed for the writing or reading of data by the CPU so that the BUSY terminals is "0".
6	BSY	DMA busy	A DMA transfer is in progress.
7 - 15		(unused)

Write Behavior

Bit(s)	Description
0 - 4	VDC register index (0-19)
5 - 15	(unused)

Address Register

A register number "AR" is exclusive written into the address register designating one of the memory address write register to DMA VRAM-SATB source address register as shown in Figures 3C to 3U so that data are writing into the video display controller(1) under the condition that the A1 and CS terminals thereof are "L".

In a case where 16 bit data bus is selected, the EX 8/16 terminal is "0", the A1 terminal is "0", the "R/W" terminal is "W", and the A0 terminal is no matter.

In a case where 8 bit data bus is selected, the EX 8/16 terminal is "1", the A0 and A1 terminals are "0", and the "R/W" terminal is "W".

Data Register

Read/Write register.

Data in the VDC register selected/indexed by the Status Register.

VRAM Registers

$00 - MAWR - Memory Address Write Register (VRAM Write Address)

A starting address "MAWR" is written into the memory address write register so that the writing of data begins at the starting address of the VRAM(7).

MAWR specifies a word offset into VRAM for writing. Subsequent writes to register $02 (VWR) will store data at the offset specified by MAWR. After each write, MAWR is incremented by the amount specified in the IW bits of CR. MAWR wraps back to zero when it's value exceeds $FFFF.

The LSB and MSB of MAWR can be updated independently of each other; accessing either half directly updates the MAWR register rather than any temporary storage. This allows quick non-sequential addressing of VRAM without having to set the entire address every time.

$01 - MARR - Memory Address Read Register (VRAM Read Address)

A starting address "MARR" is written into the memory address read register. When the upper byte of the starting address is written thereinto, data are begun to be read from the starting address of the VRAM(7) so that data thus read are written into a VRAM data read register as showing in Figure 3F. There after, the starting address "MARR" is automatically incremented by one.

MARR specifies a word offset into VRAM for reading. When the MSB is written, VRAM data from the current offset is transferred into a read buffer, and then MARR is incremented by the amount specified in the IW bits of CR. For any following VRR reads, the buffered value is immediately returned and this process repeats; the buffer is loaded from data at the current offset and MARR is incremented again.

The LSB of MARR can be updated independently of the MSB. This does not cause the buffer to be loaded, only a write to the MSB will do that.

$02 - VRR - VRAM Data Read Register

A starting address "MARR" is written into the memory address read register. When the upper byte of the starting address is written thereinto, data are begun to be read from the starting address of the VRAM(7) so that data thus read are written into a VRAM data read register as showing in Figure 3F. There after, the starting address "MARR" is automatically incremented by one.

Reading the LSB of VRR returns the LSB of the read buffer. Reading the MSB returns the MSB of the read buffer immediately, then loads the buffer with VRAM from the current offset MARR represents and increments MARR by the value specified by the IW bits of CR. To read only the MSB of multiple words, the MSB of VRR can be repeatedly read instead of reading both the LSB and MSB.

Note: when reading from VDC addresses $0002 or $0003 when VRR is not selected, the buffer will not be reloaded nor will MARR increment when the MSB is read. The buffer contents will always return the last-loaded value but never update.

$02 - VWR - VRAM Data Write Register

Data which are transferred from the CPU(2) to the VRAM(7) are written into the VRAM data write register. When the upper byte of the data "VWR" is written thereinto, the video display controller(1) begins to write the data into the VRAM(7) and the address "MAWR" of the memory address write register is automatically incremented by one upon writing of the data.

When writing to VWR, the LSB is stored in a latch rather than VRAM. Any additional writes to the LSB only update the latch contents and do not affect VRAM. When the MSB is written to, the latched LSB and new MSB data are stored to VRAM at the current offset specified by MAWR. By loading the LSB with a given value and writing to the MSB repeatedly, you can fill VRAM with a constant LSB value and variable MSB value.

$05 - CR - Control Register

Bit(s)

Description

0 - 3

(IE) enable/[o]disable[/o] interrupt flags

0

collision detection (between sprite #0 and any other sprites).

1

sprite overflow, more than 16 sprites on a scanline.

2

scanline match flag.

3

vertical blanking.

4

(EX) [o]input[/o]/output hsync signal

5

(EX) [o]input[/o]/output vsync signal

6

(SB) sprites enable/[o]disable[/o] flag

7

(BB) background enable/[o]disable[/o] flag

8 - 9

(DR) selects DISP terminal output (pin 27)

9	8	Output	DISP Content
0	0	DISP	output "H" during display
0	1	BURST	color burst inserting position is indicated by output "L"
1	0	INTHSYNC	internal horizontal synchronous signal
1	1		not used

10

(DR) dynamic RAM refresh enable/[o]disable[/o] flag

Refresh address MA0-MA15 upon setting the flag in a case where a

VRAM pixel width (see register $09) is of 2 pixels or 4 pixels in a Memory Width Register ($09)

11 - 12

read/write address auto-increment

12	11	Increment
0	0	0x01
0	1	0x20
1	0	0x40
1	1	0x80

Affect by how much are incremented the address register $00 and $01.

13 - 15

(unused)

$06 - RCR - Raster Counter Register

A raster number "RCR" at which an interruption job is performed is written into the raster detecting register. An interruption signal is produced when a value of a raster counter is equal to the raster number "RCR". The raster counter is preset to be "64" at a preceding scanning raster line to a display starting raster line as described in more detail later, and is increased at each raster line by one.

Bit(s)	Description
0 - 9	The rcr bit controls the generation of a raster counter IRQ. The VDC generates an IRQ, when the scanline specified in the RCR register is displayed. You need to add 64 to the RCR register to get the correct scanline.
10 - 15	(unused)

A raster number "RCR" at which an interruption job is performed is written into the raster detecting register. An interruption signal is produced when a value of a raster counter is equal to the raster number "RCR". The raster counter is preset to be "64" at a preceding scanning raster line to a display starting raster line as described in more detail later, and is increased at each raster line by one.

$07 - BXR - Background X-Scroll Register

The BGX scroll register is used for a horizontal scroll of background on a screen. When a content "BXR" is rewritten therein, the content is effective in the following raster line.

The value written to BXR is latched on each scanline, preventing mid-scanline changes to BXR. Further changes to BXR will not change the display until the next scanline is displayed. When the VDC generates synchronization signals this duration is in units of VDC scanlines, and when the VDC inputs external synchronization signals this is in units of VCE scanlines.

For example if the VDC displays multiple VDC scanlines in one VCE scanline, the same BXR value applies to all VDC scanlines until the current VCE scanline ends.

$08 - BYR - Background Y-Scroll Register

The BGY scroll register is used for a vertical scroll of background on a screen. When a content "BYR" is rewritten therein, the content is effective to be as "BYR+1" in the following raster line.

The value written to BYR is latched on each scanline, preventing mid-scanline changes to BYR. Further changes to BYR will not change the display until the next scanline is displayed. When the VDC generates synchronization signals this duration is in units of VDC scanlines, and when the VDC inputs external synchronization signals this is in units of VCE scanlines.

For example if the VDC displays multiple VDC scanlines in one VCE scanline, the same BYR value applies to all VDC scanlines until the current VCE scanline ends.

$09 - MWR - Memory Width Register

Character cycles

The fundamental unit of time observed by the VDC is the duration of one pixel clock cycle. The pixel clock is output by the VCE and can be any of the following:

5.3693175 MHz - ~186 ns per pixel
7.15909 MHz - ~140 ns per pixel
10.738635 MHz - ~93 ns per pixel

The VDC accesses VRAM in groups called character cycles. Each character cycle can be split into eight slots, which have a duration of one pixel clock each. The actual VRAM read or write cycle spans one or more slots, selectable in units of 1, 2, or 4 slots each.

Here's a diagram showing the number of VRAM accesses that can be made in one character cycle depending on number of slots allocated to read or write cycle:

VRAM cycle width	Slot 1	Slot 2	Slot 3	Slot 4	Slot 5	Slot 6	Slot 7	Slot 8
1 slot	1	2	3	4	5	6	7	8
2 slots	1		2		3		4
4 slots	1				2

Within the same period of time a character cycle spans, up to 8 accesses can be done when the VRAM access cycle width is 1 slot, 4 accesses can be done when cycle width is 2 slots, and only two access can be done when the cycle width is 4 slots.

The PCE uses 100ns SRAM chips as it's video RAM, so the only situation that is problematic is using a 1-cycle pixel width along with the 10.738635 MHz pixel clock. In this case each cycle is ~93 ns which violates the minimum access time requirements of the SRAM. In practice this does not cause any problems, however it does mean operating the memory 7% faster than it's guaranteed to work. This can be remedied by using a pixel width mode with longer cycles.

VRAM pixel width

The VDC will make as many sequential character cycles as the screen is wide as specified in the HDW field plus two, regardless of any horizontal scroll setting. These occur back-to-back in realtime as the display is rendered (I think there is a 1 or 2 character pipeline before any pixels are actually output). For example if the screen is 32 characters wide, 34 character cycles occur.

Bits 1, 0 of MWR set the VRAM access cycle grouping, referred to as the 'VRAM pixel width'. Bit 7 sets the character generator read mode when only two of four bitplanes can be read, due to insufficient VRAM access cycles available.

Bits 1-0 : VRAM pixel width.

D1-D0	Slot 1	Slot 2	Slot 3	Slot 5	Slot 6	Slot 7	Slot 8
00	CPU	BAT	CPU	CPU	CG0	CPU	CG1
01	BAT		CPU	CG0		CG1
10	BAT		CPU	CG0		CG1
11	BAT			CG0 / CG1

BAT is a read from the BAT region of VRAM. (word contains palette, character name)
CPU is a CPU access, either read or write.
CG0 is a read from the character generator region of VRAM. (word contains bitplane 0 and 1 bytes)
CG1 is a read from the character generator region of VRAM. (word contains bitplane 2 and 3 bytes)

The first three modes function identically. The last mode only has enough spare time in each character cycle to read CG0 or CG1, but not both. Selection of either bitplane group is done by the character generator mode bit (CM), which is bit 7 of MWR. It specifies 0= CG0 or 1= CG1. Internally, the VDC assumes the missing bitplane data is forced to zero. This means that tiles displayed when CM=0 use colors 0,1,2,3, and tiles displayed when CM=1 use colors 0,4,8,C.

Sprite pixel width

During the horizontal blanking period, the VDC fetches character generator data for the sprites (up to 16) that passed y-evaluation and have their respective data buffered in the VDC's on-chip sprite storage. The bitplane data is loaded into shift registers and will be output serially during the next scanline.

The duration of the fetch period directly relates to how much horizontal blanking time is available, as defined by the HSW, HDS, HDW, and HDE registers. If the period is too short, the process is aborted. It seems the sprites that weren't loaded have their shift registers reset to zero, as previously loaded sprite data or garbage data is not shown (this needs more testing).

Much like background rendering, bits 3-2 of MWR set the character cycle allocation for sprites, referred to as the 'Sprite pixel width'.

Bits 3-2 : Sprite pixel width.

D1-D0	Slot 1	Slot 2	Slot 3	Slot 4	Slot 5	Slot 6	Slot 7	Slot 8
00	SP0	SP1	SP2	SP3	SP0	SP1	SP2	SP3
01	SP0, SP2		SP1, SP3		SP0, SP2		SP1, SP3
10	SP0		SP1		SP2		SP3
11	SP0 / SP2				SP1 / SP3

SP0-3 are sprite bitplanes 0,1,2,3.
00b reads data for two sprites in one cycle.
01b reads data for two sprites in two cycles (bitplanes 0,1 for sprites 1,2 in cycle, bitplanes 2,3 for sprites 1,2 in the next).
10b reads data for one sprite in one cycle.
11b reads data for one sprite in one cycle, but only bitplanes 0,1 or 2,3 can be read.

Bit 0 of the pattern code field of each sprite entry specifies which bitplanes are read for a sprite pixel width setting of 11b. It can be 0= SP0,SP1 or 1= SP2,SP3. The unused bitplanes are forced to zero so that the colors used out of a 16-color palette are 0,1,2,3 when SP0,SP1 are read, or 0,4,8,C when SP2,SP3 are read.

Display Registers

$0A - HPR - Horizontal Synchronous Register

Bits 0-4 : Horizontal Sync Width (HSW)
Bits 8-14 : Horizontal Display Start (HDS)

HSW defines the width of the horizontal sync pulse in 8-pixel (character) units. The range is 1 to 32 characters.

HDS defines the interval after the horizontal sync pulse to the start of the horizontal display period in character units. The range is 1 to 128 characters.

When the VDC inputs external synchronization signals, the function of HSW changes. It no longer affects the width of the horizontal sync pulse. Instead, if during the processing of any VDC-generated scanline the HDE state expires prior to an external HSYNC pulse, the number of characters as specified by HSW are taken up before the next VDC-generated scanline starts.

This distinction is important; increasing values of HSW do not displace the horizontal display area immediately following an external HSYNC pulse, but they will for all subsequent VDC-generated scanlines before /HSYNC occurs again.

$0B - HDR - Horizontal Display Register

Bits 0-6 : Horizontal Display Width (HDW)
Bits 8-14 : Horizontal Display End (HDE)

HDW defines the width of the horizontal active display period in character units. The range is 1 to 128 characters.

HDE defines the interval following HDE to the end of the scanline, at which poinst the HSW state is entered and a horizontal sync pulse is generated. The range is 1 to 128 characters. It should be set to the remainder from the desired number of characters per scanline, minus HSW, HDS, and HDW.

$0C - VSR - Vertical Synchronous Register

Bits 0 to 4 (VSW) - vertical synchronous pulse width

A pulse width of a vertical synchronous signal is decided in a width of "L" level as a unit of a raster line. One of 1 to 32 is selected to comply with a specification of a CRT display.

Bits 8 to 15 (VDS) - vertical display starting position

A period between a rising edge of a vertical synchronous signal and a vertical synchronous starting position is set as an unit of a raster line. When it is assumed that a vertical display starting position (vertical back porch) is "N", "N-2" is written into the bits.

$0D - VDR - Vertical Display Register

A vertical display period (display region) is set as an unit of a raster line. A vertical display width is decided in accordance with the number of raster lines to be displayed on a CRT display which is defined by a content of the 9 bits. When it is assumed that a vertical display width is "N", "N-1" is written into the VDW bits.

$0E - VCR - Vertical Display Ending Postition Register

A period between a vertical display ending position and a rising edge of a vertical synchronous signal is set as an unit of a raster line. When it is assumed that a vertical optimum position (vertical front porch) is "N" to be defined by the 8 bits, "N" is written into the VCR bits.

Bits 7-0 : Vertical Display Position End (VCR)

VCR defines the interval following VDW to the end of the frame, at which point the VSW state is entered and a vertical sync pulse is generated. The range is 0 to 255 scanlines. It should be set to the remainder from the desired number of scanlines per frame, minus VSW, VDS, and VDW.

When the VDC inputs external synchronization signals, VCR should be set to a value equal to or larger than the number of scanlines the hardware generates from one edge of /VSYNC to the next. Otherwise the VDC will start generating another frame within the current display frame. This can be used to arbitrarily force additional VD interrupts and VRAM to SAT DMA transfers within a single VCE-defined frame.

DMA Registers

The Dynamic Memory Access subsystem (DMA) is the means by which the VDC reads directly from RAM.

$0F - DCR - DMA Control Register

bit 0 (DSC)	enable interruption at the completion of transfer between the VRAM and sprite attribute table buffer	0 - disable 1 - enabled
bit 1 (DVC)	Enable interruption at the completion of transfer between two regions of the VRAM	0 - disable 1 - enabled
bit 2 (SI/D)	Automatic increment or decrement of a source address selected in a transfer between two regions of VRAM	0 - disable 1 - enabled
bit 5 (DSR)	repetition of a transfer between the VRAM(7) and the sprite attribute table buffer is enabled.	0 - disable 1 - enabled

$10 - SOUR - Source Address Register

         A starting address of a source address is allocated in a transfer between two regions
         of the VRAM(7).

$11 - DESR - DMA Destination Address Register

         A starting address of a destination address is allocated in a transfer between two
         regions of the VRAM(7).

$12 - LENR - DMA Block Length Register

         A length of a block is defined in a transfer between two regions of the VRAM(7).

$13 - SATB - Sprite Attribute Table Address Register

The address of the Sprite Attribute Table. This is the only address used for access to the SATB.

VRAM Access

Typically when loading large amounts of data into VRAM the screen is turned off for several frames. In most video hardware turning the screen off stops display related DMA and gives the CPU full access to VRAM.

The VDC handles things a bit differently. BURST mode is when the color bus outputs $0100 on VD8-VD0 (sprite palette #0, color #0), display DMA is stopped (no fetching of BAT data, background patterns, sprite patterns), and the CPU has unrestricted access to VRAM regardless of the MWR settings. BURST mode is enabled in two situations:

1. Any display state outside of VDW is considered to be in the BURST mode. A possible exception is that display DMA needs to be done on line 262 or 263 (depending on the frame height) for graphics to be displayed on scanline 0.

2. If bits 7 and 6 of CR are reset prior to VDW occurring, BURST mode is forcibly entered for the entire duration of VDW. Any changes to bits 7 and 6 have no effect until the next transition into VDW, at which point they are sampled again.

Note that this means simply turning off the background and/or sprites during VDW does *not* select BURST mode, and VRAM access is still restricted. When the background is turned off during the display, the color bus outputs $0000 on VD8-VD0 (background palette #0, color #0).

To maximize VRAM throughput, it isn't necessary to force a BURST-in-VDW display condition. The duration of VDW can just be shortened to letterbox the screen and allocate more scanlines to to the other display periods, giving more BURST time.

A MWR setting of $00 gives the CPU the largest amount of access cycles (twice per 8 pixels) which seems to be exactly equal to the amount of accesses available during BURST mode.

Video Color Encoder (HuC6260)

The VCE has two functions:

supply the picture on your television.
define the location of the palettes in memory.

All VCE registers are 16 bit.

$0400 - CR - Control Register

Write only register.

Bit(s)	Description	Values
0 - 1	PCC - Pixel Clock Control	00 = 5.3693175 MHz 01 = 7.15909 MHz 10 = 10.738635 MHz 11 = 10.738635 MHz
2	Frame/Field Configuration	0 = 262-line frame 1 = 263-line frame
3 - 6	???	???
7	Strip Colorburst	0 = Colorburst intact 1 = Strip colorburst
8 - 15	(unused)

$0402 - CTA - Color Table Address Register