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User:Trap15/fm7sub: Difference between revisions

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Together with $D40E, determines VRAM access offset.<br>
Together with $D40E, determines VRAM access offset.<br>
This offset is used both for the CPU and the display.
This offset is used both for the CPU and the display.
<!-- ================================================================================ D410 -->
|-
! rowspan=1 | $D410
| RW
| ALU command register
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| EST
| M1
| M2
| colspan=2 style="background:#eaecf0" |
| colspan=3 | ALGO
|}
{| class="wikitable"
|-
! EST
| Process ALU command
| 0: Do not process<br/>1: Process
|-
! M1
| ? TODO
| ? TODO
|-
! M2
| ? TODO
| 0: Write with イコール<br/>1: Write with NOTイコール
|-
! ALGO
| ALU math algorithm
| 000: PSET<br>001: Don't Use<br>010: OR<br>011: AND<br>100: XOR<br>101: NOT<br>110: TILEPAINT<br>111: COMPARE
|}
<!-- ================================================================================ D411 -->
|-
! rowspan=1 | $D411
| RW
| ALU logical color
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=5 style="background:#eaecf0" |
| G
| R
| B
|}
<!-- ================================================================================ D412 -->
|-
! rowspan=1 | $D412
| RW
| ALU mask register
<!-- ================================================================================ D413 -->
|-
! rowspan=1 | $D413
| rowspan=8 | RW?
| rowspan=8 | ALU compare registers
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| MASK
| colspan=4 style="background:#eaecf0" |
| G
| R
| B
|}
<!-- ================================================================================ D414 -->
|-
! rowspan=1 | $D414
<!-- ================================================================================ D415 -->
|-
! rowspan=1 | $D415
<!-- ================================================================================ D416 -->
|-
! rowspan=1 | $D416
<!-- ================================================================================ D417 -->
|-
! rowspan=1 | $D417
<!-- ================================================================================ D418 -->
|-
! rowspan=1 | $D418
<!-- ================================================================================ D419 -->
|-
! rowspan=1 | $D419
<!-- ================================================================================ D41A -->
|-
! rowspan=1 | $D41A
<!-- ================================================================================ D41B -->
|-
! rowspan=1 | $D41B
| RW
| ALU bank disable register
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=4 style="background:#eaecf0" |
| 1
| G
| R
| B
|}
<!-- ================================================================================ D41C -->
|-
! rowspan=1 | $D41C
| W
| Tile paint register B
<!-- ================================================================================ D41D -->
|-
! rowspan=1 | $D41D
| W
| Tile paint register R
<!-- ================================================================================ D41E -->
|-
! rowspan=1 | $D41E
| W
| Tile paint register G
<!-- ================================================================================ END -->
<!-- ================================================================================ END -->
|}
|}

Revision as of 16:58, 9 February 2024

Sub RAM Physical Map

Start End Detail
$0000 $BFFF GVRAM
$C000 $CFFF "Console" RAM
Bankable on AV40
$D000 $D37F "Work" RAM
$D380 $D3FF Shared RAM
$D400 $D4FF Memory mapped I/O
$D500 $D7FF RAM
AV only
$D800 $DFFF Subsystem CG RAM
Other than AV40, this is ROM
$E000 $FFFF Subsystem RAM
Other than AV40, this is ROM

Sub I/O Map

Address mask depends on machine. This table goes from most to least specific. If it's not covered, fall through.

Machine Mask
AV40EX/AV40SX $FF
AV $3F
Other $0F
Address R/W Detail
$D400 R Keyboard data high bit
Bit 7 6 5 4 3 2 1 0
Name D8
D8 Keyboard data bit 8
$D401 R Keyboard data low 8 bits
Bit 7 6 5 4 3 2 1 0
Name Keyboard data bits 0~7
$D402 R Acknowledge IRQ from main CPU
$D403 R One-shot buzzer
$D404 R Send attention IRQ to main CPU
$D405 W Sub-CPU mode
Bit 7 6 5 4 3 2 1 0
Name FAST
FAST Set performance mode
Display steals cycles from CPU in Slow 		0: Fast
1: Slow

CSCP emulator implies this port interacts with the 400 line board config.

$D406 R Kanji ROM data left byte
W Kanji ROM address high byte
$D407 R Kanji ROM data right byte
W Kanji ROM address low byte
$D408 R Turn display on
W Turn display off (show only black)
$D409 R Allow access to VRAM
When in Slow performance mode, this reduces performance to ~1/3
W Disable access to VRAM
$D40A R Clear BUSY flag to main CPU
W Set BUSY flag to main CPU
$D40B RW 400-line card I/O
$D40C RW 400-line card I/O
$D40D R Turn on INS LED on keyboard (?)
W Turn off INS LED on keyboard (?)
$D40E W VRAM offset address high byte
Bit 7 6 5 4 3 2 1 0
Name OA14 OA13 OA12 OA11 OA10 OA9 OA8

OA14 only available in 400-line mode.

$D40F W VRAM offset address low byte
Bit 7 6 5 4 3 2 1 0
Name OA7 OA6 OA5 OA4 OA3 OA2 OA1 OA0

OA4~OA0 only available on L4 and AV when enabled in $D430.
Together with $D40E, determines VRAM access offset.
This offset is used both for the CPU and the display.

$D410 RW ALU command register
Bit 7 6 5 4 3 2 1 0
Name EST M1 M2 ALGO
EST Process ALU command 0: Do not process
1: Process
M1 ? TODO ? TODO
M2 ? TODO 0: Write with イコール
1: Write with NOTイコール
ALGO ALU math algorithm 000: PSET
001: Don't Use
010: OR
011: AND
100: XOR
101: NOT
110: TILEPAINT
111: COMPARE
$D411 RW ALU logical color
Bit 7 6 5 4 3 2 1 0
Name G R B
$D412 RW ALU mask register
$D413 RW? ALU compare registers
Bit 7 6 5 4 3 2 1 0
Name MASK G R B
$D414
$D415
$D416
$D417
$D418
$D419
$D41A
$D41B RW ALU bank disable register
Bit 7 6 5 4 3 2 1 0
Name 1 G R B
$D41C W Tile paint register B
$D41D W Tile paint register R
$D41E W Tile paint register G
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