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User:Trap15/fm7sub: Difference between revisions

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! rowspan=1 | $D41C
! rowspan=1 | $D41C
| W
| W
| Tile paint register B
| ALU tile paint register B
<!-- ================================================================================ D41D -->
<!-- ================================================================================ D41D -->
|-
|-
! rowspan=1 | $D41D
! rowspan=1 | $D41D
| W
| W
| Tile paint register R
| ALU tile paint register R
<!-- ================================================================================ D41E -->
<!-- ================================================================================ D41E -->
|-
|-
! rowspan=1 | $D41E
! rowspan=1 | $D41E
| W
| W
| Tile paint register G
| ALU tile paint register G
<!-- ================================================================================ D420 -->
|-
! rowspan=1 | $D420
| W
| ALU address offset register high byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=3 style="background:#eaecf0" |
| colspan=5 | A13~A9
|}
<!-- ================================================================================ D421 -->
|-
! rowspan=1 | $D421
| W
| ALU address offset register low byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=8 | A8~A1
|}
TODO
<!-- ================================================================================ D422 -->
|-
! rowspan=1 | $D422
| W
| ALU line style pattern register high byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=8 | P15~P8
|}
<!-- ================================================================================ D423 -->
|-
! rowspan=1 | $D423
| W
| ALU line style pattern register low byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=8 | P7~P0
|}
TODO
<!-- ================================================================================ D424 -->
|-
! rowspan=1 | $D424
| W
| ALU X start position high byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=6 style="background:#eaecf0" |
| colspan=2 | X9~X8
|}
<!-- ================================================================================ D425 -->
|-
! rowspan=1 | $D425
| W
| ALU X start position low byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=8 | X7~X0
|}
TODO
<!-- ================================================================================ D426 -->
|-
! rowspan=1 | $D426
| W
| ALU Y start position high byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=7 style="background:#eaecf0" |
| colspan=1 | Y8
|}
<!-- ================================================================================ D427 -->
|-
! rowspan=1 | $D427
| W
| ALU Y start position low byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=8 | Y7~Y0
|}
TODO
<!-- ================================================================================ D428 -->
|-
! rowspan=1 | $D428
| W
| ALU X end position high byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=6 style="background:#eaecf0" |
| colspan=2 | X9~X8
|}
<!-- ================================================================================ D429 -->
|-
! rowspan=1 | $D429
| W
| ALU X end position low byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=8 | X7~X0
|}
TODO
<!-- ================================================================================ D42A -->
|-
! rowspan=1 | $D42A
| W
| ALU Y end position high byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=7 style="background:#eaecf0" |
| colspan=1 | Y8
|}
<!-- ================================================================================ D42B -->
|-
! rowspan=1 | $D42B
| W
| ALU Y end position low byte
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=8 | Y7~Y0
|}
TODO
<!-- ================================================================================ D42E -->
|-
! colspan=3 |
|-
! rowspan=1 | $D42E
| W
| Sub-RAM bank select (AV40 only)
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| KNJSEL
| colspan=2 style="background:#eaecf0" |
| colspan=2 | SRA
| colspan=3 | SRB
|}
{| class="wikitable"
|-
! KNJSEL
| Select kanji ROM
| 0: Level 1<br>1: Level 2
|-
! SRA
| colspan=2 | Console RAM bank
|-
! SRB
| colspan=2 | CG RAM bank
|}
<!-- ================================================================================ D42F -->
|-
! colspan=3 |
|-
! rowspan=1 | $D42F
| W
| VRAM bank select (AV40 only)
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| colspan=6 style="background:#eaecf0" |
| colspan=2 | BS
|}
VRAM bank select (value 11 is invalid)
<!-- ================================================================================ FD30 -->
|-
! colspan=3 |
|-
! rowspan=2 | $FD30
| R
| Miscellaneous status (AV only)
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| BLANK
| colspan=2 style="background:#eaecf0" |
| BUSY
| colspan=1 style="background:#eaecf0" |
| VSYNC
| colspan=1 style="background:#eaecf0" |
| RESET
|}
{| class="wikitable"
|-
! BLANK
| Current blanking status
| 0: Blanking<br>1: Display
|-
! BUSY
| Current BUSY state
| 0: Busy<br>1: Ready
|-
! VSYNC
| Current VSYNC state
| 0: Vdisp<br>1: Vsync
|}
|-
| W
| Miscellaneous flags (AV only)
{| class="wikitable"
|-
! Bit !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
! Name
| NMIMASK
| DISPPG
| ACTPG
| colspan=2 style="background:#eaecf0" |
| OFSLOEN
| CGBANK
|}
{| class="wikitable"
|-
! NMIMASK
| NMI mask register (yes really...)
| 0: Enabled<br>1: Disabled
|-
! DISPPG
| Display page
| rowspan=2 | 0: Page 0<br>1: Page 1
|-
! ACTPG
| Active page
|-
! OFSLOEN
| Offset register OA4~OA0 enable
| 0: Disabled<br>1: Enabled
|-
! CGBANK
| colspan=2 | CG ROM bank
|}
<!-- ================================================================================ END -->
<!-- ================================================================================ END -->
|}
|}

Revision as of 18:19, 9 February 2024

Sub RAM Physical Map

Start End Detail
$0000 $BFFF GVRAM
$C000 $CFFF "Console" RAM
Bankable on AV40
$D000 $D37F "Work" RAM
$D380 $D3FF Shared RAM
$D400 $D4FF Memory mapped I/O
$D500 $D7FF RAM
AV only
$D800 $DFFF Subsystem CG RAM
Other than AV40, this is ROM
$E000 $FFFF Subsystem RAM
Other than AV40, this is ROM

Sub I/O Map

Address mask depends on machine. This table goes from most to least specific. If it's not covered, fall through.

Machine Mask
AV40EX/AV40SX $FF
AV $3F
Other $0F
Address R/W Detail
$D400 R Keyboard data high bit
Bit 7 6 5 4 3 2 1 0
Name D8
D8 Keyboard data bit 8
$D401 R Keyboard data low 8 bits
Bit 7 6 5 4 3 2 1 0
Name Keyboard data bits 0~7
$D402 R Acknowledge IRQ from main CPU
$D403 R One-shot buzzer
$D404 R Send attention IRQ to main CPU
$D405 W Sub-CPU mode
Bit 7 6 5 4 3 2 1 0
Name FAST
FAST Set performance mode
Display steals cycles from CPU in Slow 		0: Fast
1: Slow

CSCP emulator implies this port interacts with the 400 line board config.

$D406 R Kanji ROM data left byte
W Kanji ROM address high byte
$D407 R Kanji ROM data right byte
W Kanji ROM address low byte
$D408 R Turn display on
W Turn display off (show only black)
$D409 R Allow access to VRAM
When in Slow performance mode, this reduces performance to ~1/3
W Disable access to VRAM
$D40A R Clear BUSY flag to main CPU
W Set BUSY flag to main CPU
$D40B RW 400-line card I/O
$D40C RW 400-line card I/O
$D40D R Turn on INS LED on keyboard (?)
W Turn off INS LED on keyboard (?)
$D40E W VRAM offset address high byte
Bit 7 6 5 4 3 2 1 0
Name OA14 OA13 OA12 OA11 OA10 OA9 OA8

OA14 only available in 400-line mode.

$D40F W VRAM offset address low byte
Bit 7 6 5 4 3 2 1 0
Name OA7 OA6 OA5 OA4 OA3 OA2 OA1 OA0

OA4~OA0 only available on L4 and AV when enabled in $D430.
Together with $D40E, determines VRAM access offset.
This offset is used both for the CPU and the display.

$D410 RW ALU command register
Bit 7 6 5 4 3 2 1 0
Name EST M1 M2 ALGO
EST Process ALU command 0: Do not process
1: Process
M1 ? TODO ? TODO
M2 ? TODO 0: Write with イコール
1: Write with NOTイコール
ALGO ALU math algorithm 000: PSET
001: Don't Use
010: OR
011: AND
100: XOR
101: NOT
110: TILEPAINT
111: COMPARE
$D411 RW ALU logical color
Bit 7 6 5 4 3 2 1 0
Name G R B
$D412 RW ALU mask register
$D413 RW? ALU compare registers
Bit 7 6 5 4 3 2 1 0
Name MASK G R B
$D414
$D415
$D416
$D417
$D418
$D419
$D41A
$D41B RW ALU bank disable register
Bit 7 6 5 4 3 2 1 0
Name 1 G R B
$D41C W ALU tile paint register B
$D41D W ALU tile paint register R
$D41E W ALU tile paint register G
$D420 W ALU address offset register high byte
Bit 7 6 5 4 3 2 1 0
Name A13~A9
$D421 W ALU address offset register low byte
Bit 7 6 5 4 3 2 1 0
Name A8~A1

TODO

$D422 W ALU line style pattern register high byte
Bit 7 6 5 4 3 2 1 0
Name P15~P8
$D423 W ALU line style pattern register low byte
Bit 7 6 5 4 3 2 1 0
Name P7~P0

TODO

$D424 W ALU X start position high byte
Bit 7 6 5 4 3 2 1 0
Name X9~X8
$D425 W ALU X start position low byte
Bit 7 6 5 4 3 2 1 0
Name X7~X0

TODO

$D426 W ALU Y start position high byte
Bit 7 6 5 4 3 2 1 0
Name Y8
$D427 W ALU Y start position low byte
Bit 7 6 5 4 3 2 1 0
Name Y7~Y0

TODO

$D428 W ALU X end position high byte
Bit 7 6 5 4 3 2 1 0
Name X9~X8
$D429 W ALU X end position low byte
Bit 7 6 5 4 3 2 1 0
Name X7~X0

TODO

$D42A W ALU Y end position high byte
Bit 7 6 5 4 3 2 1 0
Name Y8
$D42B W ALU Y end position low byte
Bit 7 6 5 4 3 2 1 0
Name Y7~Y0

TODO

$D42E W Sub-RAM bank select (AV40 only)
Bit 7 6 5 4 3 2 1 0
Name KNJSEL SRA SRB
KNJSEL Select kanji ROM 0: Level 1
1: Level 2
SRA Console RAM bank
SRB CG RAM bank
$D42F W VRAM bank select (AV40 only)
Bit 7 6 5 4 3 2 1 0
Name BS

VRAM bank select (value 11 is invalid)

$FD30 R Miscellaneous status (AV only)
Bit 7 6 5 4 3 2 1 0
Name BLANK BUSY VSYNC RESET
BLANK Current blanking status 0: Blanking
1: Display
BUSY Current BUSY state 0: Busy
1: Ready
VSYNC Current VSYNC state 0: Vdisp
1: Vsync
W Miscellaneous flags (AV only)
Bit 7 6 5 4 3 2 1 0
Name NMIMASK DISPPG ACTPG OFSLOEN CGBANK
NMIMASK NMI mask register (yes really...) 0: Enabled
1: Disabled
DISPPG Display page 0: Page 0
1: Page 1
ACTPG Active page
OFSLOEN Offset register OA4~OA0 enable 0: Disabled
1: Enabled
CGBANK CG ROM bank
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